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LH28F008SC 1 8m (1m 8) flash memory figure 2. tsop 40-pin configuration features ? high-density symmetrically-blocked architecture C sixteen 64k erasable blocks ? high-performance C 85 ns read access time ? enhanced automated suspend options C byte write suspend to read C block erase suspend to byte write C block erase suspend to read ? enhanced data protection features C absolute protection with v pp = gnd C flexible block locking C block erase/byte write lockout during power transitions ? extended cycling capability C 100,000 block erase cycles C 1.6 million block erase cycles/chip ? low power management C deep power-down mode C automatic power saving mode decreases i cc in static mode ? automated byte write and block erase C command user interface C status register ? smartvoltage technology C 3.3 v or 5 v v cc C 3.3 v, 5 v, or 12 v v pp ? sram - compatible write interface ? etox? v nonvolatile flash technology ? industry - standard packaging C 42-pin, .67 mm 8 mm 2 csp package C 40-pin, 1.2 mm 10 mm 20 mm tsop (type i) package C 44-pin, 600-mil, sop package 28f008sc-1 top view 40-pin tsop 2 3 4 5 8 9 a 12 a 15 37 36 35 34 33 32 29 26 6 7 a 13 a 14 a 16 a 19 a 17 a 18 31 30 oe ry/by dq 6 10 11 12 39 38 we 13 28 dq 3 dq 2 dq 1 27 dq 7 14 15 16 17 18 19 20 23 25 24 22 21 a 0 a 1 a 2 a 3 a 6 a 5 a 7 a 4 a 10 a 9 a 11 a 8 nc dq 5 dq 4 v cc dq 0 40 1 nc v pp v cc rp ce gnd gnd 28f008sc-20 top view 42-pin csp a 5 a a 8 a 11 v pp a 12 a 15 a 17 1234567 a 4 a 7 a 10 v cc a 18 a 13 nc a 6 a 9 rp ce a 14 a 16 a 19 a 3 dq 1 nc v cc dq 4 dq 7 nc a 2 a 0 dq 3 gnd dq 6 oe nc a 1 b c d e f dq 0 dq 2 gnd dq 5 ry/by we figure 1. csp 42-pin configuration
LH28F008SC 8m (1m 8) flash memory 2 figure 3. sop 44-pin configuration v cc voltage v pp voltage 3.3 v 3.3 v, 5 v, 12 v 5 v 5 v, 12 v introduction sharps LH28F008SC flashfile? memory with smartvoltage technology is a high-density, low-cost, non- volatile, read/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flex- ible voltage and extended cycling provide for highly flex- ible component suitable for resident flash arrays, simms and memory cards. its enhanced suspend capabilities pro- vide for an ideal solution for code and data storage appli- cations. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F008SC offers three levels of protection: absolute protection with v pp at gnd, selective hardware block locking, or flexible software block locking. these alternatives give designers ultimate control of their code security needs. the LH28F008SC is manufactured on sharps 0.4 m etox? v process technology. it comes in in- dustry-standard packages: the 40-pin tsop, ideal for board constrained applications, and the rugged 44-pin sop. based on the 28f008sa architecture, the LH28F008SC enables quick and easy upgrades for designs demanding the state-of-the art. new features the LH28F008SC smartvoltage flashfile memory maintains backwards-compatiblity with sharps 28f008sa. key enhancements over the 28f008sa include: ? smartv oltage t echnology ? enhanced suspend capabilities ? in-system block locking both devices share a compatible pinout, status reg- ister, and software command set. these similarities enable a clean upgrade from the 28f008sa to LH28F008SC. when upgrading, it is important to note the following differences: ? because of new feature support, the two devices have different device codes. this allows for soft- ware optimization. ?v pplk has been lowered from 6.5 v to 1.5 v to support 3.3 v and 5 v block erase, byte write, and lock-bit configuration operations. designs that switch v pp off during read operations should make sure that the v pp voltage transitions to gnd. ? to take advantage of smartvoltage technology, allow v pp connection to 3.3 v or 5 v. description the LH28F008SC is a high-performance 8m smart- voltage flashfile memory organized as 1m of 8 bits. the 1m of data is arranged in sixteen 64k blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in figure 5. smartvoltage technology provides a choice of v cc and v pp combinations, as shown in the voltage combi- nations table, to meet system performance and power expectations. 3.3 v v cc consumes approximately one- fourth the power of 5 v v cc . but, 5 v v cc provides the highest read performance. v pp at 3.3 v and 5 v elimi- nates the need for a separ ate 12 v converter, while v pp = 12 v maximizes block erase and byte write per- formance. in addition to flexible erase and program volt- ages, the dedicated v pp pin gives complete data protection when v pp v pplk . v cc and v pp voltage combinations offered by smartvoltage technology 28f008sc-2 top view 44-pin sop 2 3 4 5 8 9 a 6 a 9 41 40 39 38 37 36 33 30 6 7 a 7 a 8 a 10 v pp a 11 rp 35 34 10 11 12 43 42 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 13 32 nc nc we 31 14 15 16 17 18 19 20 27 29 28 26 25 ry/by dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 dq 0 21 22 24 23 dq 4 v cc gnd gnd a 2 a 1 a 3 a 0 ce oe 44 1 v cc nc a 4 nc a 5 nc nc
8m (1m 8) flash memory LH28F008SC 3 figure 4. LH28F008SC block diagram output buffer identifier register data register status register input buffer a 0 - a 19 dq 0 - dq 7 address latch i/o logic data comparator write state machine ry/by rp oe we ce program/ erase voltage switch y-gating output multiplexer y-decoder x-decoder command register input buffer . . . address counter rp v cc v pp gnd 16 64kb blocks 28f008sc-3 inter nal v cc and v pp detection circuitry automati- cally configures the device for optimized read and write operations. a command user interface (cui) serves as the in- terface between the system processor and internal op- eration of the device. a valid command sequence written to the cui initiates device automation. an inter nal write state machine (wsm) automatically executes the algo- rithms and timings necessary for block erase, byte write, and lock-bit configuration operations. a block erase operation erases one of the devices 64k blocks typically within 1 second (5 v v cc , 12 v v pp ) independent of other blocks. each block can be inde- pendently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 6 s (5 v v cc , 12 v v pp ). byte write sus- pend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. lock-bit configuration operations (set block, lock-bit, set master lock-bit, and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsms block erase, byte write, or lock-bit configuration operation is finished.
LH28F008SC 8m (1m 8) flash memory 4 pin description symbol type name and function a 0 - a 19 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. dq 0 - dq 7 input/output data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce ? input chip enable: activates the devices control logic input buffers, decoders, and sense amplifiers. ce ? high deselects the device and reduces power consumption to standby levels. rp ? input reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp ? high enables normal operation. when driven low, rp ? inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. rp ? at v hh enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp ? = v hh overrides block lock-bits thereby enabling block erase and byte write operation to locked memeory blocks. block erase, byte write, or lock-bit configuration with v ih < rp ? < v hh produce spurious results and should not be attempted. oe ? input output enable: gates the devices outputs during a read cycle. we input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we pulse. ry ? /by ? output ready/busy: indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase, byte write, or lock-bit configuration). ry ? /by ? high indicates that the wsm is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. ry ? /by ? is always active and does not float when the chip is deselected or data outputs are disabled. v pp supply block erase/byte write, lock-bit configuration power supply: for erasing array blocks, writing bytes, or configuring lock-bits. with v pp v lko , memory contents cannot be altered. block erase, byte write, and lock-bit configura- tion with an invalid v pp (see dc characteristics) produce spurious results and should not be attempted. v cc supply device power supply: internal detection configures the device for 3.3 v or 5 v operation. to switch from one voltage to another, ramp v cc down to gnd and then ramp v cc to the new voltage. do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any pins nc no connect: lead is not internal connected; it may be driven or floated.
8m (1m 8) flash memory LH28F008SC 5 the ry ? /by ? output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry ? /by ? minimizes both cpu overhead and system power consumption. when low, ry ? /by ? indicates that the wsm is performing a block erase, byte write, or lock-bit configuration. ry ? /by ? high indicates that the wsm is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power- down mode. the access time is 85 ns (t avav ) over the commer- cial temperature range (0c to +70c) and v cc supply voltage range of 4.75 v - 5.25 v. at lower v cc voltages, the access times are 90 ns (4.5 v - 5.5 v) and 120 ns (3.0 v - 3.6 v). the automatic power savings (aps) feature substan- tially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typi- cal i ccr current is 1 ma at 5 v v cc . when ce ? and rp ? pins are at v cc , the i cc cmos standby mode is enabled. when the rp ? pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection dur- ing reset. a reset time (t phqv ) is required from rp ? switching high until outputs are valid. likewise, the de- vice has a wake time (t phel ) from rp ? -high until writes to the cui are recognized. with rp ? at gnd, the wsm is reset and the status register is cleared. the device is available in 40-pin tsop (thin small outline package, 1.2 mm thick) and 44-pin sop (small outline package). pinouts are shown in figures 1 and 2. principles of operation the LH28F008SC smartvoltage flashfile memory includes an on-chip wsm to manage block erase, byte write, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies dur- ing block erasure, byte write, and lock-bit configuration, and minimal processor overhead with ram-like inter- face timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and out- put disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erasure, byte writing, and lock-bit configuration. all functions associ- ated with altering memory contentsCblock erase, byte write, lock-bit configuration, status, and identifier codes- are accessed via the cui and verified through the sta- tus register. commands are written using standard microproces- sor write timings. the cui contents serve as input to the wsm, which controls the block erase, byte write, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, inter- nal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. this code is copied to and ex- ecuted from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend al- lows sytem software to suspend a block. byte write sus- pend allows system software to suspend a byte write to read data from any other flash memory array location. fffff f0000 effff e0000 dffff d0000 cffff c0000 bffff b0000 affff a0000 9ffff 90000 8ffff 80000 7ffff 70000 6ffff 60000 5ffff 50000 4ffff 40000 3ffff 30000 2ffff 20000 1ffff 10000 0ffff 00000 64kb block 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 64kb block 28f008sc-4 figure 4. memory map
LH28F008SC 8m (1m 8) flash memory 6 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to v pph1/2/3 . the device accommodates either design prac- tice and encourages optimization of the processor- memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout v oltage v lko or when rp ? is at v il . the devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read information can be read from any block, identifier codes, or status register independent of the v pp volt- age. rp ? can be at either v ih or v hh . the first task is to write the appropriate read mode command (read, array, read identifier codes, or read status register) to the cui. upon initial device power- up or after exit from deep power-down mode, the de- vice automatically resets to read array mode. four control pins dictate the data flow in and out of the com- ponent: ce ? , oe ? , we ? , and rp ? . ce ? and oe ? must be driven active to obtain data at the outputs. ce ? is the device selection control, and when active enables the selected memory device. oe ? is the data output (dq 0 - dq 7 ) control and when active drives the selected memory data onto the i/o bus. we ? must be at v ih and rp ? must be at v ih or v hh . figure 15 illustrates a read cycle. output disable with oe ? at a logic-high level (v ih ), the device otuputs are disabled. output pins dq 0 - dq 7 are placed in a high-impedance state. standby ce ? at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 - dq 7 outputs are placed in a high- impedance state independent of oe ? . if deselected dur- ing block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. deep power-down rp ? at v il initiates the deep power-down mode. in read modes, rp ? -low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp ? must be held low for a minimum of 100 ns. time t phqv is required after return from power- down until initial memory access outputs are valid. af- ter this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, byte write, or lock-bit configura- tion modes, rp ? -low will abort the operation. ry ? /by ? remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp ? goes to logic-high (v ih ) before an- other command can be written. as with any automated device, it is important to assert rp ? during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, byte write, or lock- bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing sta- tus information instead of array data. sharps flash memories allow proper cpu initialization following a system reset through the use of the rp ? input. in this application, rp ? is controlled by the same reset sig- nal that resets the system cpu. read identifier codes operation the read identifier codes operation outputs the manu- facturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 5). using the manufacturer and de- vice codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting.
8m (1m 8) flash memory LH28F008SC 7 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v pp = v pph1/2/3 , the cui additionally controls block era- sure, byte write, and lock-bit configuration. the block erase command requires appropriate com- mand data and an address within the block to be erased. the byte write command requires the command and address of the location to be written. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we ? and ce ? are active. the address and data needed to execute a command are latched on the rising edge of we ? or ce ? (whichever goes high first). standard microprocessor write timings are used. figures 16 and 17 illustr ate we ? and ce ? con- trolled write operations. command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, or blocks are enabled. placing v pph1/2/3 on v pp enables successful block erase, byte write and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. the command definitions table defines these commands. read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, byte write or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or byte write suspend command. the read array com- mand functions independently of the v pp voltage and rp ? can be v ih or v hh . 00000 00001 10000 10001 1ffff 10003 10004 f0001 f0002 f0000 fffff f0003 f0004 10002 00002 00003 00004 0ffff block 15 lock configuration code (blocks 2 through 14) block 1 lock configuration code reserved for future implementation reserved for future implementation reserved for future implementation reserved for future implementation reserved for future implementation master lock configuration code block 0 lock configuration code device code manufacturer code block 0 block 1 block 15 28f008sc-5 . . . . . . figure 5. device identifier code memory map
LH28F008SC 8m (1m 8) flash memory 8 bus operations mode rp ? ce ? oe ? we address v pp dq 0 - dq 7 ry ? /by ? note read v ih or v hh v il v il v ih xxd out x 1, 2, 3 output disable v ih or v hh v il v ih v ih x x high-z x 3 standby v ih or v hh v ih x x x x high-z x 3 deep power down v il x x x x x high-z v oh 4 read identifier codes v ih or v hh v il v il v ih see figure 5 x note 5 v oh write v ih or v hh v il v ih v il xxd in x 3, 6, 7 notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2/3 for v pp . see dc characteristics for v pplk and v pph1/2/3 voltages. 3. ry ? /by ? is v ol when the wsm is executing internal block erase, byte write, or lock-bit configuration algorithms. it is v oh during when the wsm is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. 4. rp ? at gnd 0.2 v ensures the lowest deep power-down current. 5. see read identifier codes command section for read identifier code data. 6. command writes involving block erase, write, or lock-bit configuration are reliably executed when v pp = v pph1/2/3 and v cc = v cc1/2/3 . block erase, byte write, or lock-bit configuration with v ih < rp ? < v hh produce spurious results and should not be attempted. 7. refer to command definitions table for valid d in during a write operation.
8m (1m 8) flash memory LH28F008SC 9 command bus cycles req'd first bus cycle second bus cycle note oper. 1 address 2 data 3 oper. 1 address 2 data 3 read array/reset 1 write x ffh read identifier codes 3 2 write x 90hread ia id4 read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 write ba 20h write ba d0h 5 byte write 2 write wa 40h or 10h write wd 5, 6 block erase and byte write suspend 1write x b0h wa 5 block erase and byte write resume 1write x d0h 5 set block lock-bit 2 write ba 60h write ba 01h 7 set master lock-bit 2 write x 60h write x f1h 7 clear block lock bits 2 write x 60h write x d0h 8 command definitions 9 notes: 1. bus operations are defined in bus definition table. 2. x = any valid address within the device. ia = idendifier code address: see figure 5. ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. see status register for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we ? or ce ? (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see read identifier code command section for read identifier code data. 5. if the block is locked, rp ? must be at v hh to enable block erase or byte write operations. attempts to issue a block erase or byte write to locked block while rp ? is v ih . 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. if the master lock-bit is set, rp ? must be at v hh to set a block lock-bit. rp ? must be at v hh to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp ? is v ih . 8. if the master lock-bit is set, rp ? must be at v hh to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp ? is v ih . 9. commands other than those shown above are reserved by sharp for future device implementations and should not be used.
LH28F008SC 8m (1m 8) flash memory 10 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the com- mand write, read cycles from addresses shown in fig- ure 5 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see identifier code table for code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp and rp ? can be v ih or v hh . following the read identifier codes command, the following information can be read: clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 are set to '1' by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see status register). by allowing sys- tem software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status regis- ter command (50h) is written. it functions independently of the applied v pp voltage. rp ? can be v ih or v hh . this command is not functional during block erase or byte write suspend modes. block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by a block erase confirm. this com- mand sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status reg- ister data when read (see figure 6). the cpu can detect block erase completion by analyzing the output data of the ry ? /by ? or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new com- mand is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not acci- dentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to '1'. also, reliable block era- sure can only occur when v cc = v cc1/2/3 and v pp = v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to '1'. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp ? = v hh . if block erase is attempted when the corresponding block lock-bit is set and rp ? = v ih , sr.1 and sr.5 will be set to '1'. block erase operations with v ih < rp ? < v hh produce spurious results and should not be attempted. code address data manufacturer code 00000 89 device code 00001 a6 block lock configurations x0002 1 ? block is unlocked dq 0 = 0 ? block is locked dq 0 = 1 ? reserved for future use dq 1 - dq 7 master lock configuration 00003 ? device is unlocked dq 0 = 0 ? device is locked dq 0 = 1 ? reserved for future use dq 1 - dq 7 note: 1. x selects the specific block lock configuration code to be read. see figure 5 for the device identifier code memory map. identifier codes read status register command the status register may be read to determine when a block erase, byte write, or lock-bit configuration is com- plete and whether the operation completed success- fully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe ? or ce ? , whichever occurs. oe ? or ce ? must toggle to v ih before further reads to update the status register latch. the read status register command func- tions independently of the v pp voltage. rp ? can be v ih or v hh .
8m (1m 8) flash memory LH28F008SC 11 byte write command byte write is executed by a two-cycle command sequence. byte write setup (standard 40h or alternate 10h) is written, followed by a second write that speci- fies the address and data (latched on the rising edge of we ? ). the wsm then takes over, controlling the byte write and write verify algorithms internally. after the byte write sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect the completion of the byte write event by analyzing the ry ? /by ? pin or status register bit sr.7. when byte write is complete, status register bit sr.4 should be checked. if byte write error is detected, the status register should be cleared. the inter nal wsm verify only detects errors for '1's that do not success- fully write to '0's. the cui remains in read status regis- ter mode until it receives another command. reliable byte writes can only occur when v cc = v cc1/2/3 and v pp = v pph1/2/3 . in the absence of this high voltage, memory contents are protected against byte writes. if byte write is attempted while v pp v pplk , status register bits sr.4 and sr.5 will be set to '1'. suc- cessful byte write requires that the corresponding block lock-bit be cleared or, if set, that rp ? = v hh . if byte write is attempted when the corresponding block lock-bit is set and rp ? = v ih , sr.1 and sr.4 will be set to '1'. byte write operations with v ih < rp ? < v hh produce spurious results and should not be attempted. block erase suspend command the block erase suspend command allows block- erase interruption to read or byte-write data in another block of memory. once the block-erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device out- puts status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to '1'). ry ? /by ? will also transition to v oh . specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is sus- pended. a byte write command sequence can also be issued during erase suspend to program data in other blocks. using the byte write suspend command (see byte wr ite suspend command section), a byte write operation can also be suspended. during a byte write operation with block erase suspended, status register bit sr.7 will return to '0' and the ry ? /by ? output will tran- sition to v ol . however, sr.6 will remain '1' to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is writ- ten to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry ? /by ? will return to v ol . after the erase resume command is written, the device au- tomatically outputs status register data when read (see figure 8). v pp must remain at v pph1/2/3 (the same v pp level used for block erase) while block erase is sus- pended. rp ? must also remain at v ih or v hh (the same rp ? level used for block erase). block erase cannot re- sume until byte write operations initiated during block erase suspend have completed. byte write suspend command the byte write suspend command allows byte write interruption to read data in other flash memory loca- tions. once the byte write process starts, writing the byte wr ite suspend command resquests that the wsm suspend the byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the byte write sus- pend command is written. polling status register bits sr.7 and sr.2 can determine when the byte write operation has been suspended (both will be set to '1'). ry ? /by ? will also transition to v oh . specification t whrh1 defines the byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is sus- pended. the only other valid commands while byte write is suspended are read status register and byte write resume. after byte write resume command is written to the flash memory, the wsm will continue the byte write process. status register bits sr.2 and sr.7 will automatically clear and ry ? /by ? will return to v ol . after the byte write resume command is written, the device automatically outputs status register data when read (see figure 9). v pp must remain at v pph1/2/3 (the same v pp level used for byte write) while in byte write sus- pend mode. rp ? must also remain at v ih or v hh (the same rp ? level used for byte write).
LH28F008SC 8m (1m 8) flash memory 12 set block and master lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a mas- ter lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. with the master lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set master lock-bit command, in con- junction with rp ? = v hh , sets the master lock-bit. after the master lock-bit is set, subsequent setting of block lock-bits requires both the set block lock-bit command and v hh on the rp ? pin. see write protection analysis table for a summary of hardware and software write protection options. set block lock-bit and master lock-bit are executed by a two-cycle command sequence. the set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). the wsm then controls the set lock- bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 10). the cpu can detect the completion of the set lock-bit event by analyzing the ry ? /by ? pin out- put or status register bit sr.7. when the set lock-bit operation is complete, status register, bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new com- mand is issued. this two-step sequence of set-up followed by execu- tion ensures that lock-bits are not accidentally set. an invalid set block or master lock-bit command will result in status register bits sr.4 and sr.5 being set to '1'. also, reliable operations occur only when v cc = v cc1/2/3 and v pp = v pph1/2/3 . in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that rp ? = v hh . if it is attempted with the master lock-bit set and rp ? = v ih , sr.1 and sr.4 will be set to '1' and the operation will fail. set block lock-bit opera- tions while v ih < rp ? < v hh produce spurious results and should not be attempted. a successful set master lock-bit operation requires that rp ? = v hh . if it is at- tempted with rp ? = v ih , sr.1 and sr.4 will be set to '1' and the operation will fail. set master lock-bit opera- tions with v ih < rp ? < v hh produce spurious results and should not be attempted. clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the master lock- bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the master lock-bit is set, clearing block lock-bits requires both the clear block lock-bits command and v hh on the rp ? pin. see write protection analysis table for a summary of hard- ware and software white protection options. clear block lock-bits operation is executed by a two- cycle command sequence. a clear block lock-bits setup is first written. after the command is written, the device automatically outputs status register data when read (see figure 11). the cpu can detect completion of the clear block lock-bits event by analyzing the ry ? /by ? pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execu- tion ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. also, a reliable clear block lock bits operation can only occur when v cc = v cc1/2/3 and v pp = v pph1/2/3 . if a clear block lock-bits operation is attempted while v pp v pplk , sr.3 and sr.5 will be set to '1'. in the absence of this high voltage, the block lock- bits content are protected against alteration. a success- ful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that rp ? = v hh . if it is attempted with the master lock-bit set and rp ? = v ih , sr.1 and sr.5 will be set to '1' and the operation will fail. a clear block lock-bits operation with v ih < rp ? < v hh produce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v pp or v cc transitioning out of valid range or rp ? active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known value. once the master lock-bit is set, it cannont be cleared.
8m (1m 8) flash memory LH28F008SC 13 wsms ess eclbs bwslbs vpps bwss dps r 76543210 sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bit status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = byte write and set lock-bit status 1 = error in byte write or set master/block lock bit 0 = successful byte write or set master/block 0 = lock-bit sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = byte write suspend status 1 = byte write suspended 0 = byte write in progress/completed sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or 1 = rp ? lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements notes: 1. check ry ? /by ? or sr.7 to determine block erase, byte write, or lock-bit configuration completion. sr.6 - sr.0 are invalid while sr.7 = '0'. 2. if both sr.5 and sr.4 are '1's after a block erase or lock- bit configuration attempt, an improper command sequence was entered. 3. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, byte write, set block/master lock-bit, or clear block lock-bits command sequences. sr.3 is not guaranteed to report accurate feedback only when v pp = v pph1/2/3 . 4. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and rp ? only after block erase, byte write, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or rp ? is not v hh . reading the block lock and master lock configu- ration codes after writing the read identifier codes com- mand indicates master and block lock-bit status. 5. sr.0 is reserved for future use and should be masked out when polling the status register. operation master lock-bit block lock-bit rp# effect block erase or byte write x 0v ih or v hh block erase and byte write enabled. 1 v ih block is locked. block erase and byte write disabled. v hh block lock-bit override. block erase and byte write enabled. set block lock bit 0xv ih or v hh set block lock-bit enabled. 1x v ih master lock-bit is set. set block lock-bit disabled. v hh master lock-bit override. set block lock-bit enabled. set master lock-bit xx v ih set master lock-bit disabled. v hh set master lock-bit enabled. clear block lock-bits 0xv ih or v hh clear block lock-bits enable. 1x v ih master lock-bit is set. clear block lock-bits disabled. v hh master lock-bit override. clear block lock-bits enabled. write protection alternatives status register definition
LH28F008SC 8m (1m 8) flash memory 14 figure 6. automated block erase flowchart start bus operation command comments write 20h block address read status register sr.7 = 0 no 1 yes suspend block erase loop 1 1 1 1 0 0 0 0 full status check if desired block erase completed block erase successful v pp range error device protect error status register data (see above) suspend block erase? sr.3 = sr.1 = write write read erase setup erase confirm data = 20h addr = within block to be erased data = d0h addr = within block to be erased status register data standby check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. bus operation command full status check procedure comments standby standby standby standby check sr.3 1 = v pp low detect check sr.1 1 = device protect detect rp = v ih block lock-bit is set only required for systems implemening lock-bit configuration check sr.4, 5 both 1 = command sequence error check sr.5 1 = block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. 28f008sc-6 write d0h block address sr.4, 5 = sr.5 = block erase error command sequence error
8m (1m 8) flash memory LH28F008SC 15 figure 7. automated byte write flowchart start bus operation command comments write 40h address read status register sr.7 = 0 no 1 yes erase suspend write loop 1 1 1 0 0 0 full status check if desired byte write completed byte write successful v pp range error device protect error read status register data (see above) suspend byte write? sr.3 = sr.1 = write write read setup byte write byte write data = 40h addr = location to be written data = data to be written addr = location to be written status register data standy check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent byte writes. sr full status check can be done after each byte write or after a sequence of byte writes. write ffh after the last byte write operation to place device in read array mode. bus operation command full status check procedure comments standby standby standby check sr.3 1 = v pp low detect check sr.1 1 = device protect detect rp = v ih block lock-bit is set only required for systems implemening lock-bit configuration check sr.4 1 = data write error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. 28f008sc-7 write byte data and address sr.4 = byte write error
LH28F008SC 8m (1m 8) flash memory 16 figure 7. block erase suspend/resume flowchart start bus operation command comments write b0h sr.7 = 0 1 0 1 block erase completed write read standby erase suspend data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy standby check sr.6 1 = erase suspended 0 = erase completed write erase resume d = d0h addr = x 28f008sc-8 write d0h read status register sr.6 = done ? byte write read byte write loop read array data read or byte write ? read array data write ffh yes no block erase resumed
8m (1m 8) flash memory LH28F008SC 17 figure 9. byte write suspend/resume flowchart start bus operation command comments write b0h sr.7 = 0 1 0 1 read array data byte write completed write read standby byte write suspend data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = byte write suspended 0 = byte write completed write read array data = ffh addr = x write byte write resume data = d0h addr = x read read array locations other than that being written. 28f008sc-9 write ffh write d0h read status register sr.2 = done reading read array data write ffh no yes byte write resumed
LH28F008SC 8m (1m 8) flash memory 18 figure 10. set block and master lock-bit flowchart start bus operation command comments write 60h block/device address sr.7 = 1 0 1 0 0 0 full status check if desired set lock-bit completed write 01h/f1h block/device address set lock-bit successful v pp range error read status register data (see above) sr.3 = write write read standby set block/master lock-bit setup set block or master lock-bit confirm data = 60h addr = block address (block), device address (master) status register data check sr.7 1 = wsm ready 0 = wsm busy data = 01h (block) f1h (master) addr = block address (block), device address (master) repeat for subsequent lock-bit set operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. bus operation command full status check procedure comments standby standby standby standby check sr.3 1 = v pp error detect check sr.1 1 = device protect detect rp = v ih (set master lock-bit operation) rp = v ih , master lock-bit is set (set block lock-bit operation) check sr.4, 5 both 1 = command sequence error check sr.4 1 = set lock-bit error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple lock-bits are set before full status is checked. if error is detected clear the status register before attempting retry or other error recovery. 28f008sc-10 read status register 0 sr.1 = sr.4, 5 = sr.4 = 1 1 command sequence error device protect error 1 set lock-bit error
8m (1m 8) flash memory LH28F008SC 19 figure 11. clear block lock-bits flowchart start bus operation command comments write 60h sr.7 = 1 0 1 yes 0 full status check if desired clear block lock-bits complete write d0h clear block lock-bits successful v pp range error read status register data (see above) sr.3 = write write read standby clear block lock-bits setup clear block lock-bits confirm data = 60h addr = x status register data check sr.7 1 = wsm ready 0 = wsm busy data = d0h addr = x write ffh after the clear block lock-bits operation to place device in read array mode. bus operation command full status check procedure comments standby standby standby standby check sr.3 1 = v pp error detect check sr.1 1 = device protect detect rp = v ih , master lock-bit is set check sr.4, 5 both 1 = command sequence error check sr.5 1 = clear block lock-bit error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attemping retry or other error recovery. 28f008sc-11 read status register yes sr.1 = sr.4, 5 = sr.5 = 1 1 command sequence error device protect error 1 clear block lock-bits error
LH28F008SC 8m (1m 8) flash memory 20 design considerations three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accom- modate multiple memory connections. three-line control provides for: ? lowest possible memory power dissipation ? complete assurance that data bus contention will not occur. to use these control input efficiently, an address decoder should enable ce ? while oe ? should be connected to all memory devices and the systems read control line. this assures that only selected memory devices have ac- tive outputs while deselected memory devices are in standby mode. rp ? should be connected to the system powergood signal to prevent unintended writes dur- ing system power transitions. powergood should also toggle during system reset. ry ? /by ? and block erase, byte write, and lock-bit configuration polling ry ? /by ? is a full cmos output that provides a hard- ware method of detecting block erase, byte write and block-bit configuration completion. it transitions low af- ter lock erase, byte write, or lock-bit configuration com- mands and returns to v oh when the wsm has finished executing the internal algorithm. ry ? /by ? can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry ? /by ? is also v oh when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby cur- rent levels, active current levels and transient peaks pro- duced by falling and rising edges of ce ? and oe ? . transient current magnitudes depend on the device out- puts capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected betw een its v cc and gnd and between its v pp and gnd. these high- frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connec- tion betw een v cc and gnd. the bulk capacitor will over- come voltage slumps caused by pc board trace inductance. v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for byte writing and block erasing. use similar trace widths and layout con- siderations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. v cc , v pp , rp ? transitions block erase, byte write and lock-bit configuration are not guaranteed if v pp falls outside of a valid v pph1/2/3 range, v cc falls outside of a v alid v cc1/2/3 range, or rp ? 1 v ih or v hh . if v pp error is detected, status register bit sr.3 is set to '1' along with sr.4 or sr.5, depending on the attempted operation. if rp ? transitions to v il during block erase, byte write, or lock-bit configu- ration, ry ? /by ? will remain low until the reset operation is complete. then, the opration will abort and the device will enter deep power-down. the aborted opera- tion may leave data partially altered. therefore, the com- mand sequence must be repeated after normal operation is restored. device power-off or rp ? transiitions to v il clear the status register. the cui latches commands issued by system soft- ware and is not altered by v pp or ce ? transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after v cc transitions below v lko . after block erase, byte write, or lock-bit configura- tion, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. power-up/down protection the device is designed to offer protection against accidental block erasure, byte writing, or lock-bit con- figuration during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we ? and ce ? must be low for a command write, driving either to v ih will inhibit writes. the cuis two-step command sequence archiecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp ? = v il regardless of its control inputs state.
8m (1m 8) flash memory LH28F008SC 21 symbol parameter min. max. unit test condition t a operating temperature 0 +70 c ambient temperature v cc 1 v cc supply voltage (3.3 v 0.3 v) 3.0 3.6 v v cc 2 v cc supply voltage (5 v 5%) 4.75 5.25 v v cc 3 v cc supply voltage (5 v 10%) 4.50 5.50 v operating conditions temperature and v cc operating conditions notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised informa- tion will be published when the product is available. veryify with your local sharp sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device bey ond the abso- lute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and ex- tended exposure beyond the operating conditions may affect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5 v on input/output pins and -0.2 v on v cc and v pp pins. during transitions, this level may undershoot to -2.0 v for periods < 20 ns. maximum dc voltage on input/output pins and v cc is v cc + 5.0 v which, during transitions, may overshoot to v cc + 2.0 v for periods < 20 ns. 3. maximum dc voltage on v pp and rp ? may overshoot to +14.0 v for periods < 20 ns. 4. output shorted for no more than on second. no more than one output shorted at a time. power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during sys- tem idle time. flash memorys nonvolatility increases usable battery life because data is retained when sys- tem power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing prod- ucts and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering rp ? to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles re- quired after rp ? is first raised to v ih . see ac character- istics - read only and write operations and figures 16 and 17 for more information. electrical specifications absolute maximum ratings* commercial oper ating t emperature during read, block erase, byte write, and lock-bit configuration ............... 0c to +70c 1 temperature under bias ...................... -10c to +80c stor age t emperature: ......................... 65c to +125c voltage on any pin (except v cc , v pp and rp ? ) ................ -2 v to +7.0 v 2 v cc supply voltage ........................... -2.0 v to +7.0 v 2 v pp update voltage during block erase, byte write ,and lock-bit configuration ............................ -2.0 v to +14.0 v 2, 3 rp ? voltage with respect to gnd during lock-bit configuration operations ...............................-2.0 v to +14.0 v 2, 3 output short circuit current .......................... 100 ma 4
LH28F008SC 8m (1m 8) flash memory 22 capacitance t a = +25c, f = 1 mhz symbol parameter typ. max. units conditions c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested. ac input/output test conditions figure 12. transient input/output reference waveform for v cc = 3.3 v 0.3 v and v cc = 5 v 5% (high speed testing configuration) figure 13. transient input/output reference waveform for v cc = 5 v 10% (standard testing configuration) 28f008sc-14 device under test note: c l includes jig capacitance 1.3 v 1n914 r l = 3.3 k w c l out figure 14. transient equivalent testing load circuit input test points output 3.0 0.0 1.5 1.5 28f008sc-12 note: ac test inputs are driven at 3.0 v for a logic '1' and 0.0 v for a logic '0'. input timing begins and output timing ends at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. input test points output 2.4 0.45 2.0 0.8 2.0 0.8 28f008sc-13 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic '1' and v ol (0.45 v ttl ) for a logic '0'. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. test configuration c l (pf) v cc = 3.3 v 0.3 v 50 v cc = 5 v 0.5% 30 v cc = 5 v 10% 100 test configuration capacitance loading value
8m (1m 8) flash memory LH28F008SC 23 dc characteristics sym. parameter v cc = 3.3 v v cc = 5 v unit test conditions note typ. max. typ. max. i li input load current 0.5 1 a v cc = v cc max., v in = v cc or gnd 1 i lo output leakage current 0.5 10 a v cc = v cc max., v out = v cc or gnd 1 i ccs v cc standby current 100 100 a cmos inputs, v cc = v cc max. ce ? = rp ? = v cc 0.2 v 1, 3, 6 22ma ttl inputs, v cc = v cc max. ce ? = rp ? = v ih i ccd v cc deep power-down current 10 10 a rp ? = gnd 0.2 v i out (ry ? /by ? ) = 0 ma 1 i ccr v cc read current 12 35 ma cmos inputs v cc = v cc max., ce ? = gnd, f = 5 mhz (3.3 v), f = 8 mhz (5 v), i out = 0 ma 1, 5, 6 14 50 ma ttl inputs, v cc = v cc max., ce ? = v ih , f = 5 mhz (3.3 v), f = 8 mhz, (5 v) i out = 0 ma i ccw v cc byte write or set lock-bit current 17 ma v pp = 3.3 v 0.3 v 1, 7 17 35 ma v pp = 5.0 v 10% 12 30 ma v pp = 12.0 v 5% i cce v cc block erase or clear block lock-bits current 17 ma v pp = 3.3 v 0.3 v 1, 7 17 30 ma v pp = 5.0 v 10% 12 25 ma v pp = 12.0 v 5% i ccws i cces v cc byte write or block erase suspend current 610ma ce ? = v ih 1, 2 i pps i ppr v pp standby or read current 15 15 a v pp v cc 1 200 200 a v pp > v cc i ppd v pp deep power-down current 55a rp ? = gnd 0.2v 1 i ppw v pp byte write or set lock-bit current 40 ma v pp = 3.3 v 0.3 v 1, 7 40 40 ma v pp = 5.0 v 10% 15 15 ma v pp = 12.0 v 5% i ppe v pp block erase or clear lock-bit current 20 ma v pp = 3.3 v 0.3 v 1, 7 20 20 ma v pp = 5.0 v 105 15 15 ma v pp = 12.0 v 5% i ppws i ppes v pp byte write or block erase suspend current 200 200 a v pp = v pph1/2/3 1
LH28F008SC 8m (1m 8) flash memory 24 dc characteristics (continued) sym. parameter v cc = 3.3 v v cc = 5 v unit test conditions note min. max. min. max. v il input low voltage -0.5 0.8 -0.5 0.8 v 7 v ih input high voltage 2.0 v cc + 0.5 2.0 v cc + 0.5 v 7 v ol output low voltage 0.4 0.45 v v cc = v cc min., i ol = 5.8 ma 3, 7 v oh 1 output high voltage (ttl) 2.4 2.4 v v cc = v cc min., i oh = 2.5 ma 3, 7 v oh 2 output high voltage (cmos) 0.85 v cc 0.85 v cc v v cc = v cc min., i oh = 2.5 a 4, 7 v cc - 0.4 v cc - 0.4 v v cc = v cc min., i oh = 100 a v pplk v pp lockout during normal operations 1.5 1.5 v v pph 1 v pp during byte write, block erase, or lock- bit operations 3.0 3.6 v v pph 2 v pp during byte write, block erase, or lock- bit operations 4.5 5.5 4.5 5.5 v v pph 3 v pp during byte write, block erase, or lock- bit operations 11.4 12.6 11.4 12.6 v v lko v cc lockout voltage 2.0 2.0 v v hh rp ? unlock voltage 11.4 12.6 11.4 12.6 v set master lock-bit override master and block lock-bit 8 notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact sharps application support hotline or your local sales office for information about typical specifications. 2. i ccws and i cces are specified with the device de-selected. if read or byte written while in erase suspend mode, the devices current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes ry ? /by ? . 4. block erases, byte writes, and lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph 1 (min.), between v pph 1 (max.) and v pph 2 (min.), between v pph 2 (max.) and v pph 3 (min.), and above v pph 3 (max.). 5. automatic power savings (aps) reduces typical i ccr to 1ma at 5 v v cc and 3 ma at 3.3 v v cc in static operation. 6. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 7. sampled, but not 100% tested. 8. master lock-bit set operations are inhibited when rp ? = v ih . block lock-bit configuration operations are inhibited when the master lock bit is set and rp ? = v ih . block erases and byte writes are inhibited when the corresponding block-lock bit is set and rp ? = v ih . block erase, byte write, and lock-bit configuration operations are not guaranteed with v ih < rp ? < v hh .
8m (1m 8) flash memory LH28F008SC 25 ac characteristics - read only operations 1 v cc = 3.3 v 0.3 v, t a = 0c to +70c symbol parameter LH28F008SC-120 LH28F008SC-150 unit note min. max. min. max. t avav read cycle time 120 150 ns t avqv address to output delay 120 150 ns t elqv ce ? to output delay 120 150 ns 2 t phqv rp ? high to output delay 600 600 ns t glqv oe ? to output delay 50 55 ns 2 t elqx ce ? to output in low z 0 0 ns 3 t ehqz ce ? high to output in high z 55 55 ns 3 t glqx ce ? to output in low z 0 0 ns 3 t ghqz oe ? high to output in high z 20 25 ns 3 t oh output hold from addresses, ce ? or oe ? change, whichever is first 00ns3 v cc = 5 v 0.5 v, 5 v 0.25 v, t a = 0c to +70c symbol parameter lh28f00sc-85 5 v cc 5% lh28f00sc-90 6 v cc 10% lh28f00sa-120 6 v cc 10% unit note min. max. min. max. min. max. t avav read cycle time 85 90 120 ns t avqv address to output delay 85 90 120 ns t elqv ce ? to output delay 85 90 120 ns 2 t phqv rp ? high to output delay 400 400 400 ns t glqv oe ? to output delay 40 45 50 ns 2 t elqx ce ? to output in low z 0 0 0 ns 3 t ehqz ce ? high to output in high z 55 55 55 ns 3 t glqx ce ? to output in low z 000ns3 t ghqz oe ? high to output in high z 10 10 15 ns 3 t oh output hold from addresses, ce ? or oe ? change, whichever is first 000ns3 notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe ? may be delayed to to t elqv - t glqv after the falling edge of ce ? without inpact on t elqv . 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). 5. see transient input/output reference waveform and tr ansient equivalent testing load circuit (high speed configuration) for testing characteristics. 6. see tr ansient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics.
LH28F008SC 8m (1m 8) flash memory 26 figure 15. ac waveforms for read operations 28f008sc-15 t avav addresses stable standby device and address selection data valid addresses (a) v ih v il ce (e) v ih v il t glqv t elqv t glqx t elqx t avqv t phqv t avel t ehqz t ghqz t oh oe (g) v ih v il we (w) v ih v il v ih v il data (d/q) (dq 0 - dq 7 ) v oh v ol v cc rp (p) high-z high-z valid output . . . . . . . . . . . . . . . . . . . . . . . . . . .
8m (1m 8) flash memory LH28F008SC 27 ac characteristics - write operations 1 v cc = 3.3 v 0.3 v, t a = 0c to +70c symbol parameter LH28F008SC-120 LH28F008SC-150 unit note min. max. min. max. t avav write cycle time 120 150 ns t phwl rp ? high recovery to we going low 1 1 s 2 t elwl ce ? setup to we going low 10 10 ns t wlwh we pulse width 50 50 ns t phhwh rp ? v hh setup to we going high 100 100 ns 2 t vpwh v pp setup to we going high 100 100 ns 2 t avwh address setup to we going high 50 50 ns 3 t dvwh data setup to we going high 50 50 ns 3 t whdx data hold from we high 5 5 ns t whax address hold from we high 5 5 ns t wheh ce ? hold from we high 10 10 ns t whwl we pulse width high 30 30 ns t whrl we high to ry ? /by ? going low 100 100 ns t whgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, ry ? /by ? high 0 0 ns 2, 4 t qvph rp ? v hh hold from valid srd, ry ? /by ? high 0 0 ns 2, 4 note: 1. see 5 v v cc ac characteristics - write operations for notes 1 through 5.
LH28F008SC 8m (1m 8) flash memory 28 ac characteristics - write operations 1 v cc = 5 v 0.5 v, 5 v 0.25 v, t a = 0c to +70c symbol parameter LH28F008SC-85 6 LH28F008SC-90 7 LH28F008SC-120 8 unit note min. max. min. max. min. max. t avav write cycle time 85 90 120 ns t phwl rp ? high recovery to we going low 1 1 1 s 2 t elwl ce ? setup to we going low 10 10 10 ns t wlwh we pulse width 40 40 40 ns t phhwh rp ? v hh setup to we going high 100 100 100 ns 2 t vpwh v pp setup to we going high 100 100 100 ns 2 t avwh address setup to we going high 40 40 40 ns 3 t dvwh data setup to we going high 40 40 40 ns 3 t whdx data hold from we high 5 5 5 ns t whax address hold from we high 5 5 5 ns t wheh ce ? hold from we high 10 10 10 ns t whwl we pulse width high 30 30 30 ns t whrl we high to ry ? /by ? going low 90 90 ns t whgl write recovery before read 00 0ns t qvvl v pp hold from valid srd, ry ? /by ? high 00 0ns2, 4 t qvph rp ? v hh hold from valid srd, ry ? /by ? high 00 0ns2, 4 notes: 1. read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to command definitions table for valid a in and d in for block erase, byte write, or lock-bit configuration. 4. v pp should be held at v pph1/2/3 (and if necessary rp ? should be held at v hh ) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5 = 0). 5. see ordering information for device speeds (valid operational combinations). 6. see transient input/output reference waveform and tr ansient equivalent testing load circuit (high seed configuration) for testing characteristics. 7. see tr ansient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characters.
8m (1m 8) flash memory LH28F008SC 29 figure 16. ac waveforms for we ? controlled write operations addresses (a) v ih v il v ih v il v ih v il v ih v il a in a in d in d in d in valid srd high-z v il v pp (v) rp (p) v pph3, 2, 1 v pplk v ih v il v ih v il v ih v hh v il t avav t avwh t whwl t wlwh t dvwh t whox t phwl t whpl t qvvl t phhwh t vpwh t qvph t whqv1, 2, 3, 4 t elwl t wheh t whgl t whax 12 3 4 5 6 notes: 1. v cc power-up and standby. 2. write block erase or byte write set-up. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. 008sc-16 ry/by (r) data (d/q) ce (e) oe (g) we (w)
LH28F008SC 8m (1m 8) flash memory 30 alternative ce ? - controlled writes 1 v cc = 3.3 v 0.3 v, t a = 0c to +70c symbol parameter LH28F008SC-120 LH28F008SC-150 unit note min. max. min. max. t avav write cycle time 120 150 ns t phel rp ? high recovery to ce ? going low 1 1 s 2 t wlel we setup to ce ? # going low 00ns t eleh ce ? pulse width 70 70 ns t phheh rp ? v hh setup to ce ? going high 100 100 ns 2 t vpeh v pp setup to ce ? going high 100 100 ns 2 t aveh address setup to ce ? going high 50 50 ns 3 t dveh data setup to ce ? going high 50 50 ns 3 t ehdx data hold from ce ? high 55ns t ehax address hold from ce ? high 55ns t ehwh we hold from ce ? high 00ns t ehel ce ? pulse width high 25 25 ns t ehrl ce ? high to ry ? /by ? going low 100 100 ns t ehgl write recovery before read 0 0 s t qvvl v pp hold from valid srd, ry ? /by ? high 0 0 ns2, 4 t qvph rp ? v hh hold from valid srd, ry ? /by ? high 0 0 ns 2, 4 note: 1. see 5 v v cc alternative ce ? controlled writes for notes 1 through 5.
8m (1m 8) flash memory LH28F008SC 31 alternative ce ? - controlled writes 1 (continued) v cc = 5 v 0.5 v, 5 v 0.25 v, ta = 0c to +70c symbol parameter LH28F008SC-85 6 LH28F008SC-90 7 LH28F008SC-120 7 unit note min. max. min. max. min . max. t avav write cycle time 85 90 120 ns t phel rp ? high recovery to ce ? going low 1 1 1 s 2 t wlel we setup to ce ? going low 000ns t eleh ce ? pulse width 50 50 50 ns t phheh rp ? v hh setup to ce ? going high 100 100 100 ns 2 t vpeh v pp setup to ce ? going high 100 100 100 ns 2 t aveh address setup to ce ? going high 40 40 40 ns 3 t dveh data setup to ce ? going high 40 40 40 ns 3 t ehdx data hold from ce ? high 555ns t ehax address hold from ce ? high 555ns t ehwh we hold from ce ? high 000ns t ehel ce ? pulse width high 25 25 25 ns t ehrl ce ? high to ry ? /by ? going low 90 90 90 ns t ehgl write recovery before read 0 0 0 s t qvvl v pp hold from valid srd, ry ? /by ? high 0 0 0 ns 2, 4 t qvph rp ? v hh hold from valid srd, ry ? /by ? high 000ns2, 4 notes: 1. in systems where ce ? defines the write pulse width (within a longer we ? timing waveform), all setup, hold, and inactive we ? times should be measured relative to the ce ? waveform. 2. sampled, not 100% tested. 3. refer to command definitions table for valid a in and d in for block erase, byte write, or lock-bit configuration. 4. v pp should be held at v pph1/2/3 (and if necessary rp ? should be held at v hh ) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5 = 0). 5. see ordering information for device speeds (valid operational combinations). 6. see transient input/output reference waveform and tr ansient equivalent testing load circuit (high seed configuration) for testing characteristics. 7. see tr ansient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics.
LH28F008SC 8m (1m 8) flash memory 32 figure 17. alternate ac waveform for ce ? controlled write operations addresses (a) v ih v il v ih v il v ih v il v ih v il a in a in d in d in d in valid srd high-z v il v pp (v) rp (p) v pph3, 2, 1 v pplk v ih v il v ih v il v ih v hh v il t avav t aveh t ehel t eleh t dveh t ehdx t phel t ehrl t qvvl t phheh t vpeh t qvph t ehqv1, 2, 3, 4 t wlel t ehwh t ehgl t ehax 12 3 4 5 6 notes: 1. v cc power-up and standby. 2. write block erase or byte write set-up. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. 008sc-17 ry/by (r) data (d/q) we (e) oe (g) ce (e)
8m (1m 8) flash memory LH28F008SC 33 figure 18. ac waveform for reset operation reset operations symbol parameter v cc = 3.3 v v cc = 5 v unit note min. max. min. max. t plph rp ? pulse low time (if rp ? is tied to v cc , this specification is not applicable) 100 100 ns t plrh rp ? low to reset during block erase, byte write, or lock-bit configuration 20 12 s 2,3 reset ac specifications 1 notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp ? is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. a reset time t phqv , is required from the latter of ry ? /by ? or rp ? going high until outputs are valid. t plph t plph t plrh rp (p) v ih v il ry/by (r) v ih v il ry/by (r) a. reset during read array mode b. reset during block erase, byte write, or lock-bit configuration v ih v il rp (p) v ih v il 28f008sc-18
LH28F008SC 8m (1m 8) flash memory 34 block erase, byte write and lock-bit configuration performance 3, 4 v cc = 3.3 v 0.3 v, t a = 0c to +70c v cc = 5 v 0.5 v, 5 v 0.25 v, t a = 0c to +70c sym. parameter v pp = 3.3 v v pp = 53 v v pp = 12 v unit note typ. 1 min. max. typ. 1 min. max. typ. 1 min. max. t whqv 1 t ehqv 1 byte write time 17 15 tbd 9.3 8.2 tbd 7.6 6.7 tbd s 2 block write time 1.1 1 tbd 0.6 0.5 tbd 0.5 0.4 tbd sec 2 t whqv 2 t ehqv 2 block erase time 1.8 1.5 tbd 1.2 1 tbd 1.1 0.8 tbd sec 2 t whqv 3 t ehqv 3 set lock-bit time 21 18 tbd 13.3 11.2 tbd 11.6 9.7 tbd s 2 t whqv 4 t ehqv 4 clear block lock-bits time 1.8 1.5 tbd 1.2 1 tbd 1.1 0.8 tbd sec 2 t whrh 1 t ehrh 1 byte write suspend latency time to read 67575 6 s t whrh 2 t ehrh 2 erase suspend latency time to read 16.2 20 9.6 12 9.6 12 s notes: 1. typical values measured at t a = +25c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. sym. parameter v pp = 53 v v pp = 12 v unit note typ. 1 min. max. typ. 1 min. max. t whqv 1 t ehqv 1 byte write time 8 6.5 tbd 6 4.8 tbd s 2 block write time 0.5 0.4 tbd 0.4 0.3 tbd sec 2 t whqv 2 t ehqv 2 block erase time 1.1 0.9 tbd 1.0 0.3 tbd sec 2 t whqv 3 t ehqv 3 set lock-bit time 12 9.5 tbd 10 7.8 tbd s 2 t whqv 4 t ehqv 4 clear block lock-bits time 1.1 0.9 tbd 1.0 0.3 tbd sec 2 t whrh 1 t ehrh 1 byte write suspend latency time to read 5645 s t whrh 2 t ehrh 2 erase suspend latency time to read 9.6 12 9.6 12 s
8m (1m 8) flash memory LH28F008SC 35 dimensions in mm [inches] maximum limit minimum limit 44sop (sop044-p-0600) 16.40 [0.646] 15.60 [0.614] 13.40 [0.528] 13.00 [0.512] 14.40 [0.567] 28.40 [1.118] 28.00 [1.102] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] typ. 44 23 22 1 3.25 [0.128] 2.45 [0.096] 44sop 2.9 [0.114] 2.5 [0.098] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 0.80 [0.031] 0 - 10 see detail detail
LH28F008SC 8m (1m 8) flash memory 36 42csp (csp042-p-0808) detail 0.10 [0.004] (see detail) 8.20 [0.323] 7.80 [0.307] 8.20 [0.323] 7.80 [0.307] 0.40 [0.016] typ. 0.67 [0.026] typ. 1.0 [1.039] typ. 1.0 [1.039] typ. 0.48 [0.019] 0.42 [0.017] 0.30 [0.012] 0.15 [0.006] 1.0 [1.039] typ. 1.0 [1.039] typ. 0.25 [0.010] min. 1.20 [0.047] max. index 0.10 [0.004] dimensions in mm [inches] maximum limit minimum limit 42csp
8m (1m 8) flash memory LH28F008SC 37 ordering information dimensions in mm [inches] maximum limit minimum limit 40tsop (tsop040-p-1020) 40tsop detail see detail 1.19 [0.047] max. 0 - 10? 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 0.49 [0.019] 0.39 [0.015] 0.49 [0.019] 0.39 [0.015] 0.125 [0.005] 10.20 [0.402] 9.80 [0.386] 0.50 [0.020] typ. 0.25 [0.010] 0.15 [0.006] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] 0.18 [0.007] 0.08 [0.003] 1 20 21 40 t 40-pin, 1.2 mm x 10 mm x 20 mm tsop (type i) (tsop040-p-1020) n 44-pin, 600-mil sop (sop044-p-0600) b 42-pin, .67 mm x 8 mm 2 csp (csp042-p-0808) LH28F008SC device type x package 28f008sc-19 example: LH28F008SCt-85 (1m x 8) flash memory, 85 ns, 40-pin tsop) 8m (1m x 8) flash memory -85 speed 85 access time (ns)
sharp reserves the right to make changes in specifications at any time and without notice. sharp does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. north america europe asia sharp electronics corporation microelectronics group 5700 nw pacific rim blvd., m/s 20 camas, wa 98607, u.s.a. phone: (360) 834-2500 telex: 49608472 (sharpcam) facsimile: (360) 834-8903 http://www.sharpmeg.com sharp electronics (europe) gmbh microelectronics division sonninstra? 3 20097 hamburg, germany phone: (49) 40 2376-2286 telex: 2161867 (heeg d) facsimile: (49) 40 2376-2232 life support policy sharp components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the sharp corporation. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: (07436) 5-1321 telex: labometa-b j63428 facsimile: (07436) 5-1532 warranty sharp warrants to customer that the products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. customer's exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reported the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, sharp will refund the purchase price of the product upon its return to sharp . this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than sharp . the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties of merchantability, fitness for use and fitness for a particular purpose are specifically excluded. ? ?1997 by sharp corporation reference code smt96114 LH28F008SC 8m (1m 8) flash memory

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